Bohr: We see more advantages in bulk than SOI. Bohr: For Intel, you’re right. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." This should mean that almost all games and applications should work with the graphics here, although not necessarily with the same speed you would see on a discrete graphics chip. The article "Deep Inside Intel" below with Mark Bohr, senior fellow at Intel, review the road map pertaining to a wide range of manufacturing and design issues.

SMD: Is the interconnect becoming more problematic? Intel’s 14nm process has been their most difficult process to develop yet, a fact that Intel is being very straightforward about. In short, this goes back to the improved interconnect density that was discussed earlier in this article. IBM developed their own "14HP" (14nm High-Performance) process at their East Fishkill, NY plant. By Ed Sperling PCMag Digital Group. Bohr: Yes, probably less than eight.

SMD: But if you’re at 22nm, 14nm isn’t very far away, so you’ve got to be working on the next step. Bohr: Intel is very serious about getting into the smart phone and tablet markets. You deposit indium phosphide or gallium arsenide layer on top of silicon to make a transistor on the surface. Principal Engineer and Graphics Architect Aditya Sreenivas. For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. In this case the 14nm process should deliver a roughly 1.6x increase in performance per watt, just as past processes have too. We’re developing products that support 100-watt server chips down to sub-1 watt smart phone chips. Is it still all about performance, or has power overtaken that?

Bohr: The finFET is scalable to 14nm. He said that neither the 14nm nor 10nm nodes use that technology, though he would have liked to. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.[30][31]. "64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme."

If you’re talking about execution engines in a graphics processor, clearly you want more cores. That’s our plan for the foreseeable future. We can sell our technology and make more money off what we’ve developed, and they can have some very compelling products. This could all explain why Qualcomm went with Samsung 5LPE next year. At least until Intel’s competitors start shipping their FinFET products this is going to be speculative, and doesn’t quantify how well those competing process nodes will perform. Tall cells account for almost 30% Skylake's composition and less than 1% on Apple's A8 or A9. Intel makes use of 193 nm immersion lithography with Self-Aligned Double Patterning (SADP) at the critical patterning layers. The foundry model worked well when traditional scaling was being followed and everybody knew where we were headed. These fab ramp-ups will in turn allow Intel to further increase their manufacturing capacity, with Intel projecting that they will have sufficient volume to handle multiple 14nm product ramps in H1’2015. He noted that in moving from the Haswell-Y to the Core M, Intel would have had a die that was 0.51x the size of the earlier chip had it been feature-neutral; with the additional features designed in, he said, Core M achieved die area scaling of 0.63x. I know Moore's Law is about transistor density, not performance. Samsung node has gone through a number of refinements from 14LPE (14 Low-Power Early) to 14LPP (14 Low-Power Performance) and further. Electron Devices Meeting (IEDM), 2014 IEEE International. Even some of the chief spokespeople for the foundries have said something similar. Intel's 14 nm process has gone through multiple refinements optimizing higher clock speed, higher drive current, and lower power dissipation. Moving on to the specifications and capabilities of their 14nm process, Intel has provided the minimum feature size data for 3 critical feature size measurements: transistor fin pitch, transistor gate pitch, and the interconnect pitch. We’re also continuing to drive down interconnect capacitance by employing lower-k dielectrics.



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